1. Field of Invention
Embodiments exemplarily described herein relate to semiconductor devices and methods of fabricating semiconductor devices, and more particularly to a method of fabricating FinFET devices.
2. Description of the Related Art
In the semiconductor manufacturing industry, efforts are continuously made to reduce the size of semiconductor devices. As the size of semiconductor devices decrease, the degree to which the semiconductor devices can be integrated together improves and the production yield increases. The performance of semiconductor devices desirably improves, in terms of reduced power consumption of the semiconductor device, as semiconductor devices decrease in size.
Undesirably, however, the length of channels in semiconductor devices (e.g., CMOS devices) can be shortened as the size of the semiconductor device decreases. If the channel length is excessively shortened, a short channel effect can occur, thereby decreasing semiconductor device performance. Drain induced barrier lowering (DIBL) is a typical short channel effect, and a potential barrier between the drain and source regions as the channel length is shortened. As a drain voltage increases, a depletion region around the drain region increases and an electric field of the drain region reduces a channel potential barrier so that an off-state of the semiconductor device increases or a leakage current between the source and drain regions increases.
In order to overcome the limitations described above a three-dimensional FinFETs have been developed.
FIG. 1 is a perspective view illustrating a structure of a conventional FinFET.
Referring to FIG. 1, a gate electrode 5 covers three surfaces of a fin-shaped active region 2 of a semiconductor substrate 1. A gate dielectric layer 4 is disposed between the gate electrode 5 and the fin-shaped active region 2. An isolation layer (not shown) is also provided. As shown, the conventional FinFET structure is an extending multi-gate structure and may allow improved gate control.
FIG. 2 is an enlarged longitudinal sectional view of the fin-shaped active region 2 shown in FIG. 1.
Referring to FIG. 2, gate lines 5a are formed over the fin-shaped active region 2 and the gate lines 5b extend down into an isolation layer 3 so as to contact sidewalls of the fin-shaped active region 2. As the size of the semiconductor device decreases, a distance between the gate lines 5a and 5b is reduced. In the event that a misalignment occurs, a gate line (e.g., gate line 5b), which should not otherwise contact the fin-shaped active region 2, contacts the sidewall of the active region 2 or is formed on the active region 2. Thus, when the portion of the gate line 5b penetrating the isolation layer 3 contacts the sidewall of the active region 2 as shown in FIG. 2, the transistor formed on the active region 2 will be undesirably influenced by a signal transmitted by gate line 5b. 
Often, both a FinFET and a planar MOSFET are formed together to improve an integration density of a semiconductor device. For example, a FinFET is formed in a cell region of a semiconductor device while a planar MOSFET is formed in a peripheral region of the semiconductor device. Furthermore, multiple FinFET structures may be fabricated in a semiconductor device, causing an upper surface of an active region to be uneven. Because the upper surface of the active region is uneven, the FinFET and planar MOSFET structures must be formed in the cell and peripheral regions, respectively, using separate masks. When separate masks are used to form FinFET and planar MOSFET structures, fabrication processes for the resultant semiconductor device can become undesirably complicated.